1. Field of the Invention
The present invention relates to voltage control oscillators (VCOs), and in particular, to tunable capacitance circuits for fine-tuning the frequency of the VCO.
2. Description of the Related Art
Voltage control oscillators play a critical role in many circuits, particularly wireless communication circuits. With the increased use and complexity of wireless communication devices, such circuits have become increasingly sophisticated. Common characteristics increasingly considered necessary are wide frequency tuning ranges, fast frequency settling times, and low phase noise performance.
Achieving a low phase noise VCO requires a high quality factor (Q) resonant, or “tank”, circuit. A VCO tank circuit typically consists of an inductance (L), a capacitance (C) and a negative transconductance (Gm) device. Thus, to achieve low phase noise performance, the VCO tank circuit requires the reactive devices L, C to have high quality factors Q.
Referring to FIG. 1, one example of a conventional VCO circuit 10 includes two bipolar junction transistors Q1, Q2 as the negative transconductance Gm devices, with feedback capacitances Cf1, Cf2, tank circuit inductances Lt1, Lt2, and tank circuit capacitances Ct1, Ct2, all interconnected substantially as shown. The transistors Q1, Q2 are biased by a bias voltage Vbias and driven by a tail current source 12 which sinks a tail current It through the two transistors Q1, Q2. In this circuit 10, which is a differential circuit, the differential VCO output voltage Vout appears between the collector terminals of the transistors Q1, Q2 across the resonant tank circuit components Lt1, Ct1, Lt2, Ct2.
As noted above, another important parameter is the frequency tuning range of the VCO. A large frequency tuning range is essential for most high performance frequency synthesizers. This requires the VCO to be capable of tuning its nominal, or “carrier”, frequency over a large frequency span. To achieve such tunability, a VCO typically uses a variable capacitor, generally referred to as a “varactor”. As is well known in the art, a varactor has a capacitance that changes with its tuning voltage. Capacitances Ct1 and Ct2 are varactors for which their respective capacitances are determined by the applied tuning voltage Vtune. A high performance varactor will have a large change in capacitance for a given tuning voltage range, plus a low parasitic capacitance and a high quality factor Q. A large range of capacitances over voltage in conjunction with a low parasitic capacitance directly affects the tuning range capability of the varactor, while the high quality factor Q, as noted earlier, is needed to achieve low phase noise operation.
There are two types of conventional varactors which are used in many designs and are widely supported in integrated circuits containing both bipolar and complementary metal oxide semiconductor (MOS) devices. One is referred to as MOS accumulation-mode varactor and the other is a P-N junction varactor. (Such devises are well known to one of ordinary skill in the art and need not be described in detail here).
Referring to FIG. 2A, a conventional MOS accumulation-mode varactor 20 typically includes a P-type substrate 22, into which an N-well 24 is diffused into which, in turn, two n+ regions 26 are diffused to create contacts within the N-well 24. Over the region 27 which, for a normal MOS transistor would be the channel region, an insulated layer 28 is deposited, often in the form of an oxide. Over this insulator 28 is a gate electrode 30. In accordance with well known MOS accumulation-mode varactor principles, application of a gate-to-bulk voltage Vgb produces a capacitance between the gate G and bulk B electrodes, with such capacitance being tunable, or variable, in conformance with the voltage Vgb.
Alternatively, as is well known in the art, the contact regions 26 can be formed as conventional drain and source regions with a bias voltage (e.g., 0.5 volt) applied at electrode B as desired in conformance with the particular circuit application, with the resulting gate-to-bias voltage Vgb producing a capacitance between the gate G and bias B electrodes, with such capacitance being tunable, or variable, in conformance with such voltage Vgb.
Referring to FIG. 2B, the electrical schematic symbol for the MOS accumulation-mode varactor can be depicted as shown.
Referring to FIG. 2C, the capacitance-versus-voltage (CV) curve associated with such a varactor 20 illustrates the large change in capacitance relative to the applied voltage Vgb within one example of a typical voltage tuning range of between +0.3 and +1.2 volt. (As is well known in the art, this voltage tuning range is typically narrow, as illustrated by this example, and will vary since it is dependent upon the particular semiconductor fabrication materials and processes used.) Such a large change in capacitance means the varactor has a large capacitance tuning range. However, as can be seen, such a large capacitance change exists over a small change in voltage. As a result, the ratio of the change in capacitance to the change in voltage has a high magnitude. This, in turn, in accordance with well known VCO principles, produces a high VCO gain KVCO. As is well known, a high VCO gain KVCO makes the design of a stable frequency synthesizer difficult due to the increased frequency tuning sensitivity. Accordingly, while it is desirable to have large tunable capacitance range, it is also desirable to have such a large tunable capacitance range occur over a similarly large tuning voltage range rather than a small tuning voltage range. This would lower the VCO gain KVCO and thereby decrease the frequency tuning sensitivity over tuning voltage, thereby facilitating fine tuning and stability of the final VCO circuit. Additionally, gate depletion that can occur (depending again upon the particular semiconductor fabrication materials and processes used) beyond the tuning voltage region, as shown in region 21, causes the change in capacitance to reverse, thereby further causing the MOS accumulation-mode varactor to potentially be unsuitable for fine tuning of a VCO over a large tunable voltage range.
Referring to FIG. 3A, a P-N junction varactor 40 typically includes a P-substrate 42 into which an N-well 44 is diffused into which, in turn, a p+ region 46 is further diffused. Over this, similar to the MOS accumulation-mode varactor 20 (FIG. 2A), an insulating layer 48 and electrode 50 are deposited. As is well known in the art, application of a voltage to this electrode 50 and the N-well 44 produces a capacitance which is tunable in conformance with such voltage Vnp.
Alternatively, as is well known in the art, region 44 need not necessarily be an N-well region per se, but can instead be virtually any of a number of regions of the various conventional N-type regions. What is important is the juxtaposition of P-type and N-type regions so as to provide a P-N junction.
Referring to FIG. 3B, the electrical schematic symbol can be depicted as shown.
While the P-N junction varactor has no gate depletion issues, its quality factor Q is dependent upon whether the device is driven by the tuning voltage at its P-terminal or N-terminal. The quality factor Q is higher when the device is driven at its P-terminal.
Referring to FIG. 3C, another characteristic of the P-N junction varactor is a lower range of capacitance values for a given range of tuning voltages. This causes the P-N junction varactor to have a lower capacitance tuning range, thereby producing a lower VCO gain KVCO.